1 ? fn6654.1 isl98012 1.8v input pwm step-up regulator the isl98012 is a high frequency, high efficiency step-up dc/dc regulator operated in fixed frequency pwm mode. with an integrated 1.4a mosfet, it can deliver up to 600ma output current at up to 92% efficiency. the adjustable switching frequency is up to 750khz, making it ideal for common boost applications. when shut down, it draws <1a of current. this feature, along with the minimum starting voltage of 1.8v, makes it suitable for portable equipment powered by 1 lithium ion, 3 to 4 nimh cells, or 2 cells of alkaline battery. the isl98012 is available in a 10 ld msop package, with a maximum height of 1.1mm. with proper external components, the whole converter takes less than 0.25in 2 pcb space. this device is specified for op eration over the full -40c to +85c temperature range. pinout isl98012 (10 ld msop) top view features ? up to 92% efficiency ? up to 600ma i out ?4.5v < v out < 17v ?1.8v < v in < 13.2v ? up to 750khz adjustable frequency ? <1a shutdown current ? adjustable soft-start ? low battery detection ? internal thermal protection ? 1.1mm max height 10 ld msop package ? pb-free (rohs compliant) applications ? 1.8v to 15v converters - oled ? 5v to 12v converters ? 3v to 5v and 3v to 12v converters ?tft-lcd ? portable equipment lx vdd fb ss lbo lbi en sgnd rt pgnd 1 2 3 4 10 9 8 7 5 6 ordering information part number (note) part marking package (pb-free) pkg. dwg. # isl98012iuz 98012 10 ld msop m10.118a ISL98012IUZ-T* 98012 10 ld msop m10.118a ISL98012IUZ-Tk* 98012 10 ld msop m10.118a *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet december 8, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6654.1 december 8, 2010 typical application 1 2 3 4 10 9 8 7 5 6 pgnd sgnd rt en lbi lx vdd fb ss lbo 22f 113k 10k 4.7nf 10h 56k c 3 10f v in (1.8v to 9v) v out (15v up to 200ma) 20nf c 10 r 1 r 2 d 1 c 5 5k r 4 0.1f c 4 c 1 l 1 r 3 en 1.8v to 12v isl98012
3 fn6654.1 december 8, 2010 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a . absolute maxi mum ratings (t a = +25c) thermal information fb, ss, rt, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v, 6.5v lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v, +18v vdd, en, lbi, lbo . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v, +12v maximum operating conditions maximum operating frequency. . . . . . . . . . . . . . . . . . . . . . . 750khz minimum operating frequency . . . . . . . . . . . . . . . . . . . . . . . 380khz thermal resistance (typical, note 1) ja (c/w) 10 lead msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature: . . . . . . . . . . . . . . . . . . . . . +135c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications v in = 5v, v out = 12v, l = 10h, i out = 0ma, r t = 56k , t a = +25c, unless otherwise specified. parameter description conditions min typ max unit v in input voltage range r 4 must ensure v dd 12v 1.8 13.2 v v out output voltage range note 2 4.5 17 v iq1 quiescent current - shut-down v en = 0, feedback resistors disconnected 1 a iq2 quiescent current v en = 2v, continuous operation 1.4 2 ma v fb feedback voltage 1.29 1.33 1.37 v i fb feedback input bias current 0 < v fb < 1.5v 0.10 a d max maximum duty cycle 89.5 92 % i lim current limit - max peak input current 1 1.4 a i en enable input bias current 1a v lbi lbi threshold voltage 180 220 250 mv v ol-lbo lbo output low i lbo = 1ma 0.1 0.2 v i leak-lbo lbo output leakage current v lbi = 250mv, v lbo = 5v 0.02 2 a r ds(on) switch on resistance at 12v output 220 m i leak-switch switch leakage current lx = 18v 1 a v out / v in /v out line regulation 3v < v in < 6v, v out = 12v, no load 0.4 %/v v out /v out load regulation i out = 50ma to 150ma 1 % i ss soft start current 0 < v ss < 0.1v 12 a v rt voltage at r t for bias current r t = 56k 1.34 v f osc1 switching frequency r t = 56k 600 670 750 khz vhi_en en input high threshold 1.6 v vlo_en en input low threshold 0.5 v note: 2. minimum v out of 4.5v is tested with v in = 1.8v. isl98012
4 fn6654.1 december 8, 2010 block diagram pin descriptions pin number pin name pin function 1 pgnd power ground; connected to the sour ce of internal n-channel power mosfet 2 sgnd signal ground; ground reference for all the control ci rcuitry; needs to have only a single connection to pgnd 3 rt timing resistor to adjust the osc illation frequency of the converter. re sistor value on rt pin determines frequency. range varies from r t = 49.9k for 750khz and r t = 100k for 380khz 4 en chip enable; connects to logic hi (>1.6v) for chip to function 5 lbi low battery input; connects to a sensing volt age, or connect to gnd if function is not used 6 lbo low battery detection output; connected to the open drain of a mosfet; able to sink 1ma current 7 ss soft-start; connects to a capacitor to control the start-up of the converter. during start-up, v ss controls the current limit and hence the in-rush current. 8 fb voltage feedback input; needs to connect to resistor divider to decide v o 9 vdd control circuit positive supply 10 lx inductor drive pin; connected to the dr ain of internal n-channel power mosfet - + start-up oscillator thermal shut-down - + i lout pwm logic r t en lbo lbi fb v dd lx sgnd pgnd ss max_duty v ref v ramp 220mv 113k 10k v out = 15v 10h v in 0.2 80m 7.2k 12a pwm comparator reference generator 56k 20nf 10f 22f 4.7nf 0.1f 5k isl98012
5 fn6654.1 december 8, 2010 typical performance curves figure 1. efficiency vs i out , v o = 15v figure 2. efficiency vs i out , v in = 3.3v, v o = 5v figure 3. efficiency vs i out , v in = 5v, v o = 12v figure 4. i dd vs f s figure 5. f s vs v dd figure 6. f s vs r t 60 70 80 90 0 50 100 150 200 250 300 i out (ma) efficiency (%) v in @ 1.8v v in @ 3.3v 92 90 88 86 84 82 80 0 100 200 300 400 500 600 700 i out (ma) efficiency (%) 94 92 90 88 86 84 82 80 78 0 100 200 300 400 500 600 i out (ma) efficiency (%) 300 400 500 600 700 800 frequency (khz) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 i dd (ma) v dd = 10v, v o = 12v to 17v continuous mode 750 200 0 56 9 12 v dd (v) f s (khz) 710 811 r t = 51.1k r t = 71.5k r t = 100k r t = 200k 30 40 50 60 70 80 40 60 80 100 120 r (k ) frequency (khz) v dd = 10v isl98012
6 fn6654.1 december 8, 2010 figure 7. steady state operation (inductor discontinuous conduction), v in = 3.3v, v o = 15v, i o < 1ma figure 8. steady state operation (inductor continuous conduction), v in = 3.3v, v o = 15v, i o = 30ma figure 9. steady state operation (inductor discontinuous conduction), v in = 5v, v o = 12v, i o = 30ma figure 10. steady state operation (inductor continuous conduction), v in = 5v, v o = 12v, i o = 300ma figure 11. power-up, v in = 3.3v, v o = 15v, i o = 30ma figure 12. power-up, v in = 5v, v o = 12v, i o = 300ma typical performance curves (continued) output ripple input ripple lx ilx output ripple input ripple lx ilx v in v lx v o i l 50mv/div 10v/div 20mv/div 0.5a/div 1.0s/div v in v lx v o i l 50mv/div 10v/div 20mv/div 0.5a/div 1.0s/div ilx v in v o i l 2v/div 5v/div 0.5a/div 0.5ms/div isl98012
7 fn6654.1 december 8, 2010 applications information the isl98012 is a fixed frequency step-up pulse-width modulation (pwm) regulator. the input voltage range is 1.8v to 13.2v and output voltage range is 4.5v to 17v. the switching frequency (up to 750khz) is decided by the resistor connected to rt pin. start-up during start-up, as v dd reaches a threshold of about 1.6v, a start-up oscillator generates a fi xed duty-ratio of 0.5 to 0.7 at a frequency of several hundred khz. this will boost the output voltage. when v dd reaches about 3.7v, the pwm comparator takes over control. the duty ratio will be decided by the least of the multiple-input direct summing comparator, the max_duty signal (about 92% duty-ratio), or the current limit comparator. soft-start is provided by ramping up the current limit comparator. an internal 12a current source charges the external css capacitor. the peak mosfet current is limited by the voltage on this capacito r. this in turn controls the rising rate of the output voltage. the regulator goes through th e same start-up sequence as well after the en signal is pulled to hi. steady-state operation when the output reaches the preset voltage, the regulator operates in steady state. depending on the input/output conditions and component values, the inductor operates in either continuous-conduction mode or discontinuous-conduction mode. in continuous-conduction mode, inductor current is a triangular waveform and lx voltage a pulse waveform. in discontinuous-conduction mode, inductor current has figure 13. load transient response 10ma to 30ma, v in = 1.8v, freq = 56.2k, v o = 15v, i o = 10ma to 30ma figure 14. load transient response, v in = 5v, v o = 12v, i o = 50ma to 300ma figure 15. output ripple, v in = 1.8v, v o = 15v, i o = 30ma figure 16. output ripple, v in = 3.3v, v o = 15v, i o = 30ma typical performance curves (continued) output load current i o v o 100ma/div 0.5v/div 0.2ms/div 10mv/div 10mv/div isl98012
8 fn6654.1 december 8, 2010 completely dried out before the mosfet is turned on again. the input voltage source, the inductor, and the mosfet and output diode parasitic capacitors form a resonant circuit. oscillation will occur in this period. this oscillation is normal and will not affect regulation. at very low load, the mosfet will skip pulses sometimes; this is normal. current limit the mosfet current limit is nominally 1.4a and guaranteed 1a. this restricts the maximum output current i omax based on equation 1: where: ? i l is the inductor peak-to-peak current ripple and is decided by equation 2: ? d is the mosfet turn-on ratio and is decided by equation 3: ?f s is the switching frequency table1 gives typical values: component considerations it is recommended that c in is larger than 10f. theoretically, the input capacitor has a ripple current of i l . due to high-frequency noise in the circuit, the input current ripple may exceed the theoretical value. a larger capacitor will reduce the ripple further. the inductor has peak and average current decided by equations 4 and 5: the inductor should be chosen to handle this current. furthermore, due to fixed inte rnal compensation, it is recommended that maximum in ductance of 10h and 15h be used in the 5v and 12v or higher output voltage, respectively. the output diode has an average current of i o and peak current is the same as the inductor's peak current. a schottky diode is recommended and it should be able to handle those currents. the output voltage ripple can be calculated as equation 6: where: ?c o is the output capacitance. ? the esr is the output capacitor esr value. low esr capacitors should be used to minimize output voltage ripple. multila yer ceramic capacitors (x5r and x7r) are preferred for output capacitors since they have a low esr and small packages. tantalum capacitors also can be used, but they take more board space and have higher esr. a minimum of 22f output capacitor is sufficient for high output current application. for lower output current, the output capacitor can be smalle r, like 4.7f. the capacitor should always have enough voltage rating. in addition to the voltage rating, the output capacitor should also be able to handle the rms current, which is given by equation 7: output voltage an external resistor divider is required to divide the output voltage down to the nominal reference voltage. the current drawn by the resistor network should be limited to maintain the overall converter efficienc y. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network less than 300k is recommended. table 1. max continuous output currents v in (v) v o (v) l (h) f s (khz) i omax (ma) 2 5 10 750 360 2 9 10 750 190 2 12 10 750 140 3.3 5 10 750 600 3.3 9 10 750 310 3.3 12 10 750 230 5 9 10 750 470 5 12 10 750 340 9 12 10 750 630 12 15 10 750 670 i omax 1 i l 2 -------- ? ?? ?? v in v o --------- = (eq. 1 ) i l v in l --------- d f s ---- - = (eq. 2) d v o v in ? v o ----------------------- - = (eq. 3) i lpk i lavg i l 2 -------- + = (eq. 4) i lavg i o 1d ? ------------- = (eq. 5) v o i o d f s c o --------------------- - i lpk esr + = (eq. 6) i corms 1 ( d ) d i l 2 i lavg 2 ------------------- - + ? ? ? ? 1 12 ------ ? ? ? ? ? i lavg = (eq. 7) isl98012
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6654.1 december 8, 2010 the boost converter output voltage is determined by the relationship in equation 8: where v fb slightly changes with v dd . rc filter the maximum voltage rating for the vdd pin is 12v. an rc filter is recommended to clean the output ripple before bootstrapping the part. for bootstrapped applications with v out greater than 10v, r 4 can drop v out for coupling into the vdd pin and is given by equation 9: where i dd is shown in the i dd vs f s curve. otherwise, r 4 can be 10 to 51 with c 4 = 0.1f. thermal performance the isl98012 uses a fused-lead package, which has a reduced ja of +100c/w on a four-layer board and +115c/w on a two-layer board. maximizing copper around the ground pins will improve the thermal performance. this chip also has internal thermal shut-down set at around +135c to protec t the component. layout considerations the layout is very important for the converter to function properly. power ground ( ) and signal ground ( ) should be separated to ensure that the high pulse current in the power ground never interferes with the sensitive signals connected to signal ground. th ey should only be connected at one point. the trace connected to pin 8 (fb) is the most sensitive trace. it needs to be as short as possible and in a ?quiet? place, preferably between pgnd or sgnd traces. in addition, the bypass capacitor connected to the vdd pin needs to be as close to the pin as possible. the heat of the chip is mainly dissipated through the sgnd pin. maximizing the copper area around it is preferable. in addition, a solid ground plane is always helpful for the emi performance. the demo board is a good exampl e of layout based on these principles. please refer to the isl98012 technical brief for the layout. http://www.intersil. com/data/tb/tb429.pdf v out v fb 1 r 2 r 1 ------ - + ?? ?? ?? = (eq. 8) r 4 v o 10 ? i dd -------------------- - = (eq. 9) isl98012
10 fn6654.1 december 8, 2010 isl98012 package outline drawing m10.118a (jedec mo-187-ba) 10 lead mini small outline plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop10l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to amse y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view gauge plane 33 0.25 0.25 c a b a b 0.10 c 0.08 c a b 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 5.80 3.00 4.40 0.50 0.30 1.40 pin# 1 id 1 2 10 detail "x" seating plane 0.5 bsc 0.23 +0.07/ -0.08 3.0 0.1 4.9 0.15 3.0 0.1 0.10 0.05 0.86 0.09 side view 2 included. included.
|
